Technical Field: This disclosure is related to analog to digital and digital to analog conversion.
Related Art: Wireless and wireline communications continue to grow today. Applications in wireless communications today may support multi-mode operation, utilize large portions of network bandwidth, for example, in UltraWideBand and 60-GHz-band systems, as well as attempt to re-use a licensed spectrum. To support this high-demand environment, a high dynamic range of operation for Analog to Digital Converters (ADCs) is desirable. Conventional ADCs however are inefficient because they may consume a significant portion of wireless communication chips power, for example, in some instances the ADCs may consume almost ⅓ or more of the total available power.
Wireline (or wired) communication systems also continue to demand increase in data throughput, for example, in Ethernet or next-generation cable modems. Wireline communications supporting the PAM4 (where PAM means “Pulse Amplitude Modulation”) modulation standards are being proposed for high speed serial interconnect, network protocol link layers for example, Ethernet, InfiniBand, Serial Attached SCSI (Small Computer System Interface) and Fibre Channel. These applications are also driving demand for high resolution, high-speed, low power, and low cost integrated ADCs.
In today's system-on-chip (SoC) implementations, power consumption is one important performance and design parameter. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated development of power-efficient analog, radio-frequency and digital integrated circuits (ICs). Technology scaling may lower the cost of digital logic and memory and there is an incentive to implement high-volume baseband signal processing using the latest available process technology. There is significant interest in using transistors with minimum channel length and minimum oxide thickness to implement analog functions, because improved device transition frequency, allows for faster operations. However, device scaling may adversely affect other parameters relevant to analog designs. To achieve high linearity, high sampling speed, high dynamic range, with low supply voltages and low power dissipation in ultra-deep submicron CMOS (Complementary Metal-Oxide Semiconductor) technology is a major challenge.
Conventional ADC architectures attempt to achieve high conversions rates at undesirable high power consumption levels and conversion latency. Continuous efforts are being made to improve performance of ADCs at desirable power consumption levels.